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AHB to Wishbone Bridge: Overview Details Name: ahb2wishbone Created: 31-Jul-2007 15:17:26 Updated: 07-Sep-2007 11:32:24 CVS: browse Other project properties Category :: SoC Language :: Verilog Phaze :: Design done Phaze :: FPGA proven Phaze :: Specification done Standard :: Wishbone compliant core Development status :: Mature Project maintainers TooMuch Semiconductor Solutions Statistics view Description AHB Protocol to Wishbone Protocol Bridge. Features AHB 2.0 compliant Wishbone B.3 compliant AHB Burst NOT SUPPORTED Fully synthesisable Synchronous Verilog RTL Includes a Verilog Testbench with 10 Testcases Status RTL : Complete Testbench : Complete Document : Complete