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AES128: Overview Details Name: aes_crypto_core Created: 07-Dec-2004 13:09:04 Updated: 28-Dec-2004 06:31:08 CVS: browse Other project properties Category :: Crypto core Language :: VHDL License :: LGPL Phaze :: Design done Development status :: Production/Stable Project maintainers Hemanth Satyanarayana Statistics view Description This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core is developed for a key size of 128 bits and operates in ECB mode. The project contains a synthesizable RTL along with a Test Bench set up to verify the Core with test vectors as described in the FIPS document. General Features Input and Key size of 128 bits. Operation in ECB mode. Performance adheres to FIPS-197. Core with high speed and low latency. RTL and TB in VHDL. Status Core verified in simulation and uploaded.