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A VHDL CAN Protocol Controller: Overview Details Name: a_vhdl_can_controller Created: 23-Aug-2007 20:12:18 Updated: 03-Nov-2007 03:31:50 CVS: no files in cvs Other project properties Category :: Communication controller Language :: VHDL Phaze :: Design done Development status :: Production/Stable Project maintainers George Huber Statistics view Description A (as far as I know) untested VHDL translation of the Verilog Can protocol Controller To Download, click at the "Downloads" button upper right part of this page This project is a translation Igor Mohor's Verilog CAN Protocol Controller Features The modules have "_vhdl_" added to their names, to ease compare simulation with Verilog version (for those with mixed a language simulator) Status use at own risk - have no had time to test/simulate check the Philips SJA1000 data sheet and the Verilog project page for more information