LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Downloads :: Tracker :: Discussions (cores)    

    a VHDL 8254 Timer: Overview

    Details

    Name: a_vhdl_8253_timer
    Created: 03-Aug-2008 18:13:04
    Updated: 24-Aug-2008 17:44:51
    CVS: no files in cvs

    Other project properties

    Category :: Other
    Dependencies :: Other cores
    Language :: VHDL
    Phaze :: Design done
    Development status :: Production/Stable

    Project maintainers

  • Howard A. LeFevre
  • Statistics

  • view
  • Description

    a VHDL version of the Intel 8254 timer.

    Note: uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.

    Design assumes asynchronous interface/counter clocks – includes Boolean generics (for each counter) if the same clock is used for interface and counter, or if the clocks are synchronous (different frequency, but with aligned rising edges)

    To down load project, click on "Downloads" on the tool bar, top of this page.

    Features

    Uses parts from the gh_vhdl_library project

    Status

    added version with AMBA APB interface 16 Aug 2008


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.