LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Downloads :: Tracker    

    8051 core: Overview

    Details

    Name: 8051
    Created: 25-Sep-2001 10:15:02
    Updated: 29-Jul-2008 23:57:07
    CVS: browse

    Other project properties

    Category :: Microprocessor
    Standard :: Wishbone compliant core
    Development status :: Alpha

    Project maintainers

  • Jaka Simsic
  • Simon Teran
  • Statistics

  • view
  • Description

    The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory.

    Features

    • 8-bit CPU optimized for control applications
    • Exstensive Boolean processing (single-bit logic) capabilities
    • 64K Program Memory address space
    • 64K Data Memory address space
    • up to 64K bytes of on-chip Program Memory (ROM)
    • 128 bytes of on-chip Data RAM
    • 4, 8 bit wide, ports outputs (byte or bit addressable)
    • 4, 8 bit wide, ports inputs (byte or bit addressable)
    • Two 16-bit timer/counters
    • 6-source/5-vector interrupt structure with two priority levels priority levels

    Status

    Basic core is now syntesizable. I test it with XESS XSV board.
    It have all pheripherals.

    I/O ports

    • rst (in) reset
    • clk (in) clock
    • int0 (in) external interrupt 0
    • int1 (in) external interrupt 1
    • ea (in) external access
    • iadr_o (out) program rom addres
    • idat_i (in) input from external rom
    • istb_o (out) strobe to program rom
    • iack_i (in) acknowledge from external rom
    • icyc_o (out) cycle output to external rom
    • dat_i (in) exteranal ram input
    • dat_o (out) exteranal ram output
    • adr_o (out) external address
    • we_o (out) write to external ram
    • stb_o (out) strobe
    • ack_i (in) acknowledge
    • cyc_o (out) cycle
    • p0_in, p1_in, p2_in, p3_in (in) port inputs
    • p0_out, p1_out, p2_out, p3_out (out) port outputs
    • rxd (in) receive
    • txd (out) transmit
    • t0, t1 (in) t/c external inputs


    interface

    Modules

    • oc8051_acc: accumulator
    • oc8051_alu: aritmetic logic unit
    • oc8051_alu_src1_sel, oc8051_alu_src2_sel, oc8051_alu_src3_sel: alu source select modules
    • oc8051_b_register: sfr b register
    • oc8051_comp: compare
    • oc8051_cy_select: carry select
    • oc8051_decoder: main module, decodes instruction and creates control signals
    • oc8051_defines
    • oc8051_divide: alu submodule for division
    • oc8051_dptr: data pointer register
    • oc8051_ext_addr_sel: external address select
    • oc8051_immediate_sel: innediate data select
    • oc8051_indi_addr: indirect address select
    • oc8051_int: interrupt handling module
    • oc8051_multiply: alu submodule for multiplection
    • oc8051_op_select: operation select
    • oc8051_pc: program counter
    • oc8051_ports: port inputs and outputs
    • oc8051_psw: program status word
    • oc8051_ram_top: data ram
    • oc8051_ram_rd_sel: select address for reading from ram
    • oc8051_ram_sel: ram output select
    • oc8051_ram_wr_sel: select address for writing to ram
    • oc8051_regX: X wide registers (used to dely signal for 1 clock)
    • oc8051_rom: program rom
    • oc8051_rom_addr_sel: rom address select
    • oc8051_sp: stack pointer
    • oc8051_tc: timer/counter
    • oc8051_timescale
    • oc8051_top: top module
    • oc8051_uart: serial interface


    design diagram


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.