Overview :: News :: Downloads :: Tracker :: Discussions (cores)

3DES (Triple DES) / DES (VHDL): Overview Details Name: 3des_vhdl Created: 27-Oct-2006 22:55:12 Updated: 01-Dec-2006 14:00:09 CVS: browse Other project properties Category :: Crypto core Language :: VHDL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Daniel Socek Statistics view Description This is a VHDL implementation of Triple-DES (pipelined) and DES cryptographic algorithms, as recommended by NIST. In our tests the core has been verified to comply with the NIST FIPS 46-3 (DES)recommendation. This core is provided by: Coretex Systems, LLC Features Pipelined architecture. VHDL source code. Verified in hardware. Small footprint (the numbers are for Xilinx Virtex 2 FPGA) 1742 slices, 302 IOBs, no block RAMs, 1 GCLK. Fast processing (the numbers assume the pipeline is fully utilized) An output each 17 clocks. Maximum operating frequency 162 MHz. Bandwidth ~581 Mb/s. Status The code is verified, documentation to be added. We are working on an extension to support the Wishbone interface.