wb_size_bridge :: Overview
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Details
Name: wb_size_bridge
Created: Mar 16, 2009
Updated: Feb 4, 2010
SVN Updated: Jan 30, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Memory core
Language: Verilog
Development status: Stable
Additional info:
Design done, FPGA proven
WishBone Compliant: Yes
License:
Overview
This IP provides a 8-bit or 16-bit bridge for a 32-bit WishBone interface. There is no buffering. The 32-bit transaction is delayed until the transaction is complete. An example using the wb_size_bridge is included that interfaces to an asynchronous memory. The asynchronous memory module has configurable setup times, hold times, and big/little endian support.