2D FHT :: Overview
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Details
Name: two_dimensional_fast_hartley_transform
Created: May 1, 2009
Updated: Dec 16, 2009
SVN Updated: Jun 20, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Arithmetic core
Language: Verilog
Development status: Alpha
Additional info:
FPGA proven
WishBone Compliant: No
License: LGPL
Description
RTL Verilog code of the Two Dimensional Fast Hartley Transform (2D-FHT) algorithm with decimation in frequency domain is presented.
Main Features
Discrete Hartley Transform is used in a wide variety of signal processing applications such as filtering, convolution, correlation, compression and so on.
The most popular usage of the Hartley Transform is image processing applications.
Functional Description
The N-point Discrete Hartley Transform is given by the next formula:
where
RTL Verilog code which is presented here was designed to calculate 2D-FHT (8x8 points) algorithm with decimation in frequency domain.
Block Diagram
Implementation Result
| Xilinx FPGA | Slices | DSP48 | BRAM | Freq., MHz |
|---|---|---|---|---|
| Virtex-4 xc4vlx60 | 818 | 4 | 1 | 200 |
Status
RTL Verilog release of the Two Dimensional Fast Hartley Transform Algorithm.
Verilog RTL - 1st version released. Refer to repository for latest revision.
Verification - If you have any question please feel free to send me message.
Testbench - If you have any question please feel free to send me message.
Documentation - If you have any question please feel free to send me message.