SystemC/Verilog Random Number Generator :: Overview
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Details
Name: systemc_rng
Created: Aug 19, 2004
Updated: Mar 20, 2008
SVN Updated: No data
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Latest version: download
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Other project properties
Category: Other
Language: Verilog
Development status: Stable
Additional info:
FPGA proven
WishBone Compliant: No
License: LGPL
Description
A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statisticall properties.
Based on the Thomas E. Tkacik work available at:
http://ece.gmu.edu/crypto/ches02/talks_files/Tkacik.pdf
This work is given by Universidad Rey Juan Carlos (Spain)
www.escet.urjc.es/~jmartine