Request(s)
Bug(s)
| Date |
Title |
Status |
Assigned to |
Submitted by |
| Mar 5, 2010 |
wrong copy/paste |
OPENED |
|
cbeguet |
| Mar 4, 2010 |
Missing Library |
OPENED |
|
cbeguet |
| Jul 3, 2009 |
blocking and non-blocking |
CLOSED |
rherveille |
markman |
| Jun 1, 2009 |
WISHBONE Bus captures write data twice. |
CLOSED |
rherveille |
rehayes |
| Apr 30, 2009 |
extra SCL tick |
OPENED |
rherveille |
stustuff123 |
| Feb 12, 2009 |
Arbitration error in (vhdl) version 1.17 of the i2c_master_bit_ctrl |
CLOSED |
rherveille |
awijsmuller |
| Jan 29, 2009 |
project lists under VHDL ...but no VHDL |
DELETED |
rherveille |
poppafuze |
| Jan 20, 2009 |
scl_oen? |
DELETED |
rherveille |
olaf.vandenberg |
| Nov 3, 2008 |
Strange I2C behavior (reads->writes) |
CLOSED |
rherveille |
galland |
| Aug 9, 2008 |
Repeated Start Tsu |
OPENED |
rherveille |
vackovik@yahoo.com |
| Jul 26, 2008 |
Clock synchronization for multi-master system |
CLOSED |
rherveille |
ivanlawrow@yahoo.com |
| Apr 9, 2008 |
Lacking example and erroneous example? |
CLOSED |
|
wzab@ise.pw.edu.pl |
| May 25, 2007 |
START doesn't satisfy Timing Requirements? |
CLOSED |
rherveille |
jeremy.hannon@ge.com |
| Aug 4, 2004 |
testbench error |
CLOSED |
rherveille |
kelvin_bao@163.com |
| Feb 10, 2004 |
Testbench error |
CLOSED |
rherveille |
martin.j.thompson@trw.com |
Idea(s)
© copyright 1999-2010
OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.