Floating Point Adder and Multiplier :: Overview
Project maintainers
Details
Name: fpuvhdl
Created: Jun 18, 2004
Updated: Dec 20, 2009
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Arithmetic core
Language: VHDL
Development status: Stable
Additional info:
Design done, FPGA proven
WishBone Compliant: No
License:
Description
This Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU repository, or downloaded as a separate file from the FP units home page.
The FP Adder is a single-precision, IEEE-754 compilant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 385 CLBs and with a theoretical maximum operating frecuency of 6MHz for the single-cycle design and 87MHz for the pipelined design. The design was tested at 33MHz.
The FP Multiplier is a single-precision, IEEE-754 compilant, signed multiplier. It includes both single-cycle and 4-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 119 CLBs and with a theoretical maximum operating frecuency of 8MHz for the single-cycle design and 90MHz for the pipelined design. The design was tested at 33MHz.
Features
- IEEE-754 compilant
- 32 bits, single precision
- Works with normalized and unnormalized numbers
- Simple block design, good for FP arithmetic learning
- Adder
- 385 CLBs
- 87 MHz, 6-stage pipelined
- Multiplier
- 119 CLBs
- 90 MHz, 4-stage pipelined