Name: fast_log
Created: Oct 10, 2009
Updated: Dec 20, 2009
SVN: No files checked in
Category: Arithmetic core
Language: Verilog
Development status: Planning
Additional info:
none
WishBone Compliant: No
License: LGPL
A fast (single-cycle) base-2 log function, based on the description at http://www.cantares.on.ca/extras.html
I will upload versions as time permits (Verilog and VHDL) - feel free to add your own implementations.