DDR SDRAM Controller Core :: Overview
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Details
Name: ddr_sdr
Created: Dec 20, 2002
Updated: Feb 1, 2010
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Category: Memory core
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Development status: Stable
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WishBone Compliant: No
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Description
The DDR SDRAM Controller provides the user with a simplified
interface to industry standard memory devices.
Using this controller makes accesses to DDR SDRAM devices
as simple as possible.
Initialization and auto refresh are automatically done
by the controller. Two major commands are sufficient
for most applications : READ and WRITE.
The controller has been designed for the XILINX Virtex II
family of FPGA's and can be reconfigured to provide a solution
customized to the user's needs of system and memory-specific
requirements.
Features
- up to 100 (133) MHz system clock frequency in -4 (-5) speed grade
- BURST LENGTH : 2
- CAS latency : 2
- Commands : NOP, READ, WRITE
- Automatic, configurable Auto Refresh
- Automatic precharge/activate when changing ROW/BANK
- All main parameters are configurable
- Unidirectional DQS signals (only for write operations)
- Data mask signals not used
- Runs with the Micron MT46V16M16 without changes