AHB to Wishbone Bridge :: Overview
Overview

Details

Name: ahb2wishbone
Created: Jul 31, 2007
Updated: Dec 20, 2009
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: SoC
Language: Verilog
Development status: Mature
Additional info: Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License:

Description

AHB Protocol to Wishbone Protocol Bridge.

Features

- AHB 2.0 compliant
- Wishbone B.3 compliant
- AHB Burst NOT SUPPORTED
- Fully synthesisable
- Synchronous
- Verilog RTL
- Includes a Verilog Testbench with 10 Testcases

Status

- RTL : Complete
- Testbench : Complete
- Document : Complete

© copyright 1999-2010 OpenCores.org, equivalent to ORSoC AB, all rights reserved. OpenCores®, registered trademark.