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Personal page of Vladimir V.Erokhin, PhD
| Username | vladvas |
| Fullname | Vladimir V.Erokhin, PhD |
| Email | vladvas@d... |
| City | Moscow |
| Country | Russia |
| Account created | 02-Mar-2003 14:23:39 |
| Last logged in | 16-Nov-2005 12:53:28 |
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Skils
- 5 years experience as project manager;
- 7 years experience as a Designer using Synopsys & Cadence, including development of synthesizable VHDL & Verilog code, synthesis and debugging.
- 7 years experience as a hardware designer including development of processors structure, development of processor and periphery blocks, BIST blocks, real tests development, chip testing;
- 12 years experience in microcontrollers (hardware & software) development;
- 25 years experience in Software development for CAD and other applications.
Projects
Single Clock Unsigned Division Algorithm
Preface
Now two division algorithms are wide spread in computing: restoring and non-restoring algorithms. They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during one clock.
However there are no principle objections against getting all digits of the quotient and the remainder during one clock. So the author tried to develop such kind of algorithm.
Restoring algorithm is seemed to be sequential in nature because during remainder restoring there is positive feedback (A=A – B + B at the same cycle). To avoid the feedback it is necessary to insert register for intermediate result storing.
Thus, non-restoring algorithm was chosen as basic for single-clock division algorithm.
HIERARCHICAL Integer Multiplier unit
One of the Implementations of Completely Asyncronous unsigned(signed) integer multiplication algorithms. These IPs could be embeded into any of the design where the multiplication is supposed to be done for 1 clock step, such as DSP, RISC and usual processors.
PYRAMID Integer Multiplier unit
One of the Implementations of Completely Asyncronous unsigned(signed) integer multiplication algorithms. These IPs could be embeded into any of the design where the multiplication is supposed to be done for 1 clock step, such as DSP, RISC and usual processors.
HCSA adder and Generic ALU based on HCSA
Adder is a BASE of mostly everything in the Digital World and its characteristics have a huge impact on the Digital Circuit at the whole. Hierarchical Carry Save Algorithm (HCSA) is a modification of one of the three well known adder algorithms. The HCSA shows good timing and low area (gate/cell count) requirements even comparable with some Synthesis built-in methods (for example Synopsys "CLA" adder).
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