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Personal page of takayuki sugawara
| Username | tak.sugawara |
| Fullname | takayuki sugawara |
| Email | sugawara@s... |
| City | sendai |
| State | miyagi |
| Country | JAPAN |
| Account created | 19-Apr-2005 13:51:59 |
| Last logged in | 25-Apr-2005 23:06:56 |
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Skils
Disk Controller ASIC Design 15years,
Wireless Controller ASIC Design 3years,
Veilog HDL Simulator Design 4years
Projects
YACC-Yet Another CPU CPU
YACC (Yet Another CPU CPU) is MIPS I (TM) subset cpu written in Verilog-2001 HDL. YACC has 5 pipeline and shows 110DMIPS in stratix2 with synthesized allowable clock of 165MHz. It is independent design of plasma, although YACC uses gcc-elf-mips tools provided by Steve Rhords, author of plasma (Most mips written in VHDL).
The core was developed by using Veritak Simulator, with post layout gate simulation, and tested by actual FPGAs, using Xilinx spartan3 starter kit and Cyclone by Altera,running 800 digits of pi calculation ,(255,223) Reed Solomon Error Correction ,and Interactive calculator written by C language.
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