Quantcast
        LOGIN   :::   RECOVER PASS   :::   FOR DEVELOPERS    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Personal page of Samuel Hangouët

    Usernameshangouet
    FullnameSamuel Hangouët
    Emailshangouet@l...
    CityRENNES
    CountryFrance
    Account created   22-Feb-2005 17:17:05
    Last logged in09-Feb-2006 18:28:56

    Skils
    VHDL, SYSTEMC ASM MIPS, ST7 ANSI C, C++ PHP, MySQL, XHTML

    Projects

  • miniMIPS
    The miniMIPS is a 5 stage pipeline based on the MIPS I instruction set which is a 32 bits RISC architecture. Nearly all the instructions are supported with some custom feaures added.
    The core has been prototyped on an FPGA during an internship.

    This project was developped during an student project from the ENSERG university in Grenoble, France.

  •  
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.