|
Personal page of Rudolf Usselmann
| Username | rudi |
| Fullname | Rudolf Usselmann |
| Email | rudi@a... |
| Account created | 25-Sep-2001 12:01:23 |
| Last logged in | 21-Jun-2007 13:03:49 |
|
|
Skils
Over 20 years of ASIC design, verification and synthesis.
Please visit http://www.asics.ws for more information
Projects
WB/OPB & OPB/WB Interface Wrapper
Interface wrappers between OPB and WISHBONE buses
AES (Rijndael) IP Core
AES (Rijndael) IP Core. Complete with cipher and inverse cipher and key expansion block. Everything written in Verilog - high performace, small area.
Generic FIFOs
Generic, multiple purpose, parameterizable FIFOs. Single and Dual Clock.
USB 1.1 Function IP Core
USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous In, 1 Isochronous Out, 1 Bulk In, 1 Bulk Out, 1 Interrupt In. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Fully tested in hardware on an XESS board.
Single Slot PCM Interface
Single Slot (Channel) PCM interface enables to exchange of PCM data with many popular devices (e.g. any TI DSP). This controller support 16 bit data, and allows the user to adjust the start of the bit stream.
Simple Asynchronous Serial Controller
Simple asynchronous serial controller with flow control
USB 1.1 PHY
This is a USB 1.1 Phy. Fully functional, has been verified in a FPGA prototype board from XESS, with an external Philips transceiver. Internal interface based on UTMI.
WISHBONE Conmax IP Core
This is a WISHBONE Interconnect Matrix IP core. It can interconnect up to 8 Masters and 16 Slaves
WISHBONE DMA/Bridge IP Core
This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
USB 2.0 Function Core
USB 2.0 compliant core which allows data transfers of 480 Mb/s.
Mini-Risc core
This is a Mini-RISC CPU/Microcontroller that is compatible with the PIC 16C57 from Microchip. Additional information about the instruction set and capabilities can be found at: www.microchip.com
Memory Controller IP Core
This is an advanced Memory Controller intended for embedded applications.
Floating Point Unit
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions.
DES/Triple DES IP Cores
Traditional DES and Triple DES IP Cores.
AC 97 Controller IP Core
This is a AC 97 Controller Core. It provides a an interface to an external AC 97 Audio Codec. This allows the implementation of CD quality Audio Input/Output.
News
OPB/WISHBONE wrappers
July 10, 2004
Success Story
USB 1.1 Function IP Core Released
|
 |
Browse
