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Personal page of Rudy Dwi Putra
| Username | rud_dp |
| Fullname | Rudy Dwi Putra |
| Email | rudy.dp@g... |
| Account created | 01-Feb-2006 12:22:47 |
| Last logged in | 29-Feb-2008 15:22:03 |
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Projects
Reed-Solomon Decoder (31, 19, 6)
Specifications:
1. Hard-decision decoding scheme
2. Codeword length (n) : 31 symbols.
3. Message length (k) : 19 symbols.
4. Error correction capability (t) : 6 symbols
5. One symbol represents 5 bit.
6. Use GF(2^5) with primitive polynomial p(x) = X^5 + X^2 + 1
7. Generator polynomial, g(x) = a^15 + a^21*X + a^6*X^2 +
a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 +
a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 +
a^24*X^11 + X^12.
Note: a = alpha, primitive element in GF(2^5) and a^i is root
of g(x) for i = 19, 20, ..., 30
8. Uses Verilog description with synthesizable RTL modelling.
9. Consists of 5 main blocks: SC (Syndrome Computation), KES
(Key Equation Solver), CSEE (Chien Search and Error
Evaluator), Controller and FIFO Register.
10. Uses 2 clock phases.
Features:
1. High speed decoder, 45.5 clock cycles to find syndrome
values and solve error evaluator and error location polynomial
from start signal until finish of KES block (43 clock cycles
without timing synchronization).
2. Can output corrected received word while input new received
word. Thus, minimizing throughput bottleneck to only in KES
block.
3. Synchronous timing
4. Have dataoutstart (start of output data block) and
dataoutend (end of output data block) signal to synchronize
to other core outside the decoder.
5. Have failure flag if error is uncorrectable.
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