|
Personal page of Richard Herveille
| Username | rherveille |
| Fullname | Richard Herveille |
| Email | richard@h... |
| City | Hulsberg |
| Country | NL |
| Account created | 25-Sep-2001 12:01:23 |
| Last logged in | 18-Jul-2008 05:13:13 |
|
|
Skils
Over 10 years of ASIC/FPGA design, synthesis and verification experience.
Visit www.asics.ws for more information.
Projects
SoC Interconnection
The WISHBONE System-on-Chip (SoC) Interconnect Architecture for Portable IP Cores is a portable interface for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration problems. This is accomplished by creating a common, logical interface between IP cores. This improves the portability and reliability of the system, and results in faster time-to-market for the end user. WISHBONE itself is not an IP core...it is a specification for creating IP cores.
SPI core
Enhanced MC68HC11 SPI core.
DragonBall/68K Wishbone interface
WISHBONE Interface for Motorola's Dragonball and 68K microprocessors.
Simple General Purpose IO
Simple General Purpose IO core.
Simple Programmable Interrupt Controller
Simple programmable Interrupt Controller. Supports 8 interrupt sources. Programmable Level/Edge sensitivity and Polarity per interrupt source.
Hardware Division Units
This is a collection of hardware divider cores.
OpenCores54x DSP
The OC54x DSP is a cleanroom implementation of a popular family of DSPs.
Video compression systems
The Video Systems project is a collection of readily available blocks to build different types of compression standards, like H.310, H.320, MPEG-1, MPEG-2 etc.
VGA/LCD Controller
The OpenCores VGA/LCD Controller core is a WISHBONE rev.B3 compliant embedded VGA core capable of driving CRT and LCD displays.
SSRAM interface
The 'SSRAM interface core' is a collection of designs for easy integration of synchronous srams (ZBT srams) in your designs.
I2C controller core
I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.
CORDIC core
The CORDIC (COordinate Rotation on a DIgital Computer) algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.
OCIDEC (OpenCores IDE Controller)
ATA (AT attachment) interface core, also known as the IDE (Integrated Drive Electronics) interface.
The ATA interface provides a simple interface to (low cost) non-volatile memories, like harddisk drives, DVD players, CD(ROM) players/writers and CompactFlash and PC-CARD devices.
News
OpenCores releases WISHBONE Rev.B3 specifications
Silicore Corporation Transferes WISHBONE Stewardship to OpenCores
|
 |
Browse
