PWM/Timer/Counter (PTC) Core PWM/Timer/Counter (PTC) IP core is a user-programmable PWM, Timer and Counter controller. Its use is to implement functions like Pulse Width Modulation (PWM), timer and counter facilities.
OpenRISC 1000 OpenRISC 1000 is an architecture of a family of open source, synthesizable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets wide range of embedded environments.
OCRP-1 board OpenCores Reference Platform 1 (OCRP-1) standalone board was designed as a common prototype platform for testing our IP cores. It has a central FPGA for evaluating and testing IP cores, I/O capabilities, DRAM and FLASH memory. It also has several I/O, JTAG and expansion connectors. It even has real-time clock and a battery. Current PCBs have four layers.
Embedded FPGA Core This core provides plural of high-speed reprogrammable logic. This FPGA has regular structure and consists of three configurable elements: Look-Up-Tables (LUTs), each with 8 inputs and 2 outputs, full 4b adders and Input-Output Cells (IOCs).
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