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Personal page of Kailas Senan
| Username | kailassenan |
| Fullname | Kailas Senan |
| Email | kailassenan@y... |
| City | Mysore |
| State | Karnataka |
| Country | IN |
| Account created | 05-Sep-2005 15:23:15 |
| Last logged in | 29-Aug-2008 07:39:36 |
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Skils
Experience in RTL coding, Simulation and Synthesis in FPGA & ASIC Design.
>Digital Design using FPGAs
>High Speed Board Design & Development
>IP Core development using VHDL
Projects
Profibus
Application entity has two different models with two different architectures:
1. DpMasterAppl - for Master Application module; 4.1.1
2. DpSlaveAppl - for Slave Application module; 4.1.2
Articles
Transaction Level Modeling(TLM)-to-RTL Design Flow
Multiclock designs in FPGA
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