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Personal page of John Clayton
| Username | jclaytons |
| Fullname | John Clayton |
| Email | jclaytons@e... |
| Account created | 25-Sep-2001 12:01:23 |
| Last logged in | 23-May-2006 23:29:42 |
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Projects
Binary to BCD conversions, with LED display driver
Modules for converting binary input to Binary Coded Decimal (BCD) output, and for converting Binary Coded Decimal input to binary output. Tested in hardware. Parameterized Verilog.
Unsigned serial divider
Parameterized module performs unsigned division operation. Parameters determine the size of the quotient, divisor and dividend. Can be used to produce fractional results as well. Takes multiple clock cycles to execute, since it uses serial operation.
Keypad Scanner
Parameterized module that scans an (X,Y) keypad matrix and reports which key is pressed. Variable scan rate, provides registered outputs.
Automatic BAUD rate generator
This module allows for RS232 serial communications (UART) to automatically synthesize a BAUD rate to match incoming serial data, regardless of the FPGA clock rate. It works by measuring the speed of the incoming characters, and producing its own clock to match. It has been tested at clock rates ranging from 1.5 MHz up to 98 MHz.
risc16f84
This logic module implements a small RISC microcontroller, with functions and instruction set very similar to those of the Microchip 16F84 chip.
This work is a translation (from VHDL to Verilog) of the "CQPIC" design published in 1999 by Sumio Morioka of Japan, and published in the December
1999 issue of "Transistor Gijutsu Magazine." The translation was performed by John Clayton, without the use of any translation tools.
Original version used as basis for translation: CQPIC version 1.00b (December 10, 2000)
NOTE: I have created a modified version of the 16f84 module, which only requires 2 clocks per instruction, and which has been tested at 49.152 MHz.
Interrupts have been implemented and tested on the latest "risc16f84_clk2x.v" version.
Memory sizer
Automatically sizes memory accesses to fit different types of memory, dynamically. You may read/write DWORDS and WORDS using BYTE wide RAM, etc. Handles little endian and big endian, misaligned accesses etc. Resizable parameterized module. Written in Verilog.
RS232 system controller
RS232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type of bus. Specifically, it lets the user write and read registers, and send out reset pulses, via an rs232 serial connection to a "dumb terminal."
PS2 interface
The PS/2 interface project (ps2_interface) is interface hardware to allow using a ps2 mouse or keyboard in your project. The code is written in Verilog, and was sythesized into a Xilinx SpartanII XC2S200 chip. Debugging was done with an HP16500 series logic analyzer, and there is no testbench for these interfaces.
News
Small risc core supports interrupts, compiles using free WebPack tools.
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