|
Personal page of Jens Gutschmidt
| Username | fpga_is_funny |
| Fullname | Jens Gutschmidt |
| Email | scantara2003@y... |
| City | Olten |
| Country | CH |
| Account created | 13-Dec-2006 09:17:04 |
| Last logged in | 01-Dec-2008 18:12:41 |
|
|
Skils
several years experience in
Tools:
- Renoir / HDL-Designer
- ModelSim VHDL
- Lattice Development Tools for CPLD
- Altera Quartus II
- TestBencherPro / Quickbench
---
Fields of activity:
- IPs (Altera, PLDA, Mentor Graphics, ...)
- translate programs for CPUs to HDL (e.g. math)
- embedded systems for Linux / NIOS2
- cryptographic designs
- translate historical designs (async) to FPGA (sync)
Projects
cpu65c02_tc - 65C02 Processor Soft Core with accurate timing
The 65C02 is the upgraded version of the legendary R6502. cpu65c02_tc offers you an accurate timing for all new and upgraded op codes of the 65C02. This soft core was generated in VHDL and designed with Mentor's HDL Designer.
It comes also with graphical views formatted in HTML to show and explain very clearly the hierarchy of the hole design.Please feel free to tell me any ideas, errors or some thing else like special functions, testbenches or documentation.
cpu6502_tc
This is a VHDL IP core with True Cycle Timing for Rockwell's 6502 8-Bit CPU. With full functional input signals like ready, interrupt, non maskable interrupt and set overflow flag. Also available is the output signal sync which signals an op fetch. The ready signal is usable for DMA operations or multiprocessing. Signal sync can be used for software/hardware debugging via single stepping (single cycles or complete op codes) the 6502.
This core was successfully tested in an APPLE ][+ SoC (completely designed into a FPGA with Z80 Softcard, DISK2 System, 80C Card, Language Card and 48kB of main memory).Please feel free to contact me for any reasons like ideas or error messages.
|
 |
Browse
