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    Personal page of Andreas Fellnhofer

    Usernamefellnhofer
    FullnameAndreas Fellnhofer
    Emailkrethiundplethi@g...
    Account created   30-Jan-2008 19:36:43
    Last logged in05-Feb-2008 11:43:10

    Projects

  • Diogenes: Student RISC System
    This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture and features

    * Assembler
    * Simulator
    * Simple I/O (Leds, Buttons, UART, LCD)
    * VGA Controller

    Please note that it was developed on a Sparten-3E Starter Kit and memory in VHDL code is embedded via XILINX specific routines.

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