The main features of HSSDRC IP core are:
1. Adaptive SDRAM bank control : command sequence is depending upon previous accesses to the RAM.
2. Adaptive command pipeline control: bank control commands for following memory access commands are pipelined into previous command processing chain whenever possible.
3. Overlapping command and data processing
4. Variable transaction burst from 1 to 16
5. Full SDRAM bandwidth usage for linear sequential access without bus turnaround, bank or row change

HSSDRC IP core and IP core testbench has been written on SystemVerilog and tested in Modelsim.

HSSDRC IP core is licensed under MIT License