|
Personal page of chad magleby
| Username | cmagleby |
| Fullname | chad magleby |
| Email | cmagleby@g... |
| Account created | 01-Dec-2007 08:53:56 |
| Last logged in | 24-Mar-2008 23:52:30 |
|
|
Skils
ASIC/FPGA RTL designer. Please see http://www.gutzlogic.com (GutzLogic) for details
Projects
PCI Express 16 bit CRC verilog file
This file will generate the LCRC for PCI Express TLP's packets.
It takes in 16 bits parallel at a time. All data of the TLP packet including the sequence number and TD bit should be passed through the CRC code.
PCI Express x1 16bit VERA testbench
This is a great starter testbench for PCI Express. It performs link management; Initial Flow control; tlp packet generation. It includes lcrc generation; scrambling/descrambling and
|
 |
Browse
