FirGen/MultGen
VHDL core generator
for FIR filters and Multiplier arrays with common input
using "Nonrecursive Signed Common Subexpression Algorithm"
for optimizationprogram writen on C++
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firgen [OPTION..]
Aviable options are :
-w Input Data Width
-m Generate Only Multipliers Array
-a Generate Asynchronus Multipliers Array
-e Use CLK_En input
-c filter coefitions
-o Output File Name
-? Help
Example For Use:
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FirGen -w 16 -c 1,2,3,4,5 -o my_fir
this command generates 2 output files
my_fir.vhd - Main Fir module
my_fir_mult.vhd - Multipliers Array
Input data width is 16 bit
Filter Coefitions : 1,2,3,4,5
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