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TIME SLOT INTERCHANGE DIGITAL SWITCH: Downloads CVS: No files in cvs Date Description Link 10-May-2004 TDM_Switch_DS.pdf TDM_Switch_DS.pdf 25-Oct-2003 Self extracting (RAR) archive of this project for ModelSim behavioral simulation ModelSim_Edition.exe 24-Aug-2003 Data for input stream 7 stream_7.dat 24-Aug-2003 Data for input stream 6 stream_6.dat 24-Aug-2003 Data for input stream 5 stream_5.dat 24-Aug-2003 Data for input stream 4 stream_4.dat 24-Aug-2003 Data for input stream 3 stream_3.dat 24-Aug-2003 Data for input stream 2 stream_2.dat 24-Aug-2003 Data for input stream 1 stream_1.dat 24-Aug-2003 Data for input stream 0 stream_0.dat 24-Aug-2003 Data file for connection memory (line 1-256) and frame delay registers (line 257-264) map.dat 24-Aug-2003 Testbench for top module testbench_top.v 24-Aug-2003 SDF annotation file for “tdm_switch_top_timesim.v” netlist tdm_switch_top_timesim.sdf 24-Aug-2003 Post Place and Route Verilog netlist file created by Xilinx ISE 5.2i for Concept NC-Verilog simulator tdm_switch_top_timesim.v 24-Aug-2003 Top module of TDM Switch for behavioral simulation tdm_switch_b.v 24-Aug-2003 Top module of Time Slot Interchange Digital Switch tdm_switch_top.v Total: 16