OR1k Start-up
An OpenRISC system can be started up in many different ways. This solutions makes it possible to have an startup application in an external FLASH togehter with initialization of peripherals such as an SDRAM controller.
Downloading OR1k Start-up
Source code for current development of the OR1k Start-up is available from the OpenCores SVN repository using:
svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1k_startup
On the OR1K family of processors the reset address is by default 0x100. On some implementations this can be changed to an arbitrary address. Since memory address 0x0 and upwards is RAM this invokes a challenge. Some systems may have non volatile memory in the form of SPI FLASH. Dependant on controller this type of memory might not be accessible to ordinary read and write operations but rather through an SPI controller. This IP do not take care of the start address, that must be the responsibility of wishbone arbiter or internal OR1K setup. If the system directs the instruction fetch to this module at startup the following will happen
- required internal registers will be set
- an optional loop will write configure data to memory addresses defined in SPI FLASH
- application code and data will be copied from external SPI FLASH to memory location 0x0 and upwards
- program execution will start at address 0x100
This IP is written in Verilog RTL and can be targeted to the following target technologies:
- Generic target independent design
- ACTEL ProASIC3
Typical setup with IPs included in OR1K_startup marked with *:
