Overview
Details
Name: or1k
Created: Sep 25, 2001
Updated: Feb 1, 2010
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Processor
Language: Verilog
Development status: Stable
Additional info:
ASIC proven, Design done, FPGA proven, Specification done
WishBone Compliant: Yes
License: LGPL
Introduction
The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform must be versatile to fit various target applications. Platform is based on three main ingredients:
- free, open source 32/64-bit RISC/DSP architecture
- set of free, open source implementations of the architecture
- complete set of free, open source software development tools, operating systems and software applications/libraries
However the OpenRISC project does not impose any restrictions on third parties to create their own proprietary implementations of the OpenRISC 1000 architecture or port their own software development tools, operating systems and applications to the OpenRISC.
The OpenRISC 1000 architecture is the latest in the development of modern open architectures and the base for a family of 32- and 64-bit RISC/DSP processors. Open architecture allows a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. Designed with emphasis on performance, simplicity, low power consumption, scalability, and versatility, it targets medium and high performance networking, portable, embedded, and automotive applications.
Wishlist (TODO List)
This is what we would like to see developers/contributers help us with, send an email to openrisc_team@opencores.org if you want to contribute.
- 1. Linux 2.6 port improvements
- 2. Demo Applications using OpenRISC Technology
- 3. Ports of Commercial Software Development Tools
- 4. Ports of Commercial Operating Systems (including RTOSes)
- 5. Port/Optimization of various DSP libraries (G.7xx codecs etc.)
- 6. RedHat eCos Port
If you have a suggestion for new Wishlist entry, feel free to send it to openrisc_team@opencores.org.
Project Maintainers
This project is maintained by
Past Contributor(s)
These are the people currently not working on the OpenRISC, but have contributed allot in the past:- Damjan Lampret, Johan Rydberg, Chen-Min Chen, Greg McGary, Chris Ziomkowsi, Marko Mlinar, Simon Srot, Matan Ziv-Av, Balint Cristian, Matjaz Breskvar, and many more.....