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Message
From: Víctor López<victor.lopez@o...>
Date: Wed Jul 30 16:48:32 CEST 2008
Subject: [oc] How do YOU implement WISHBONE regs' access and why?
Hello everybody, Usually in my projects I avoid complications when implementing the
Wishbone bus and regs by using a double port memory (DP-RAM) to store
the reg contents: one port for the WB bus and the other for my core's
exclusive use.
I recently studied the Ethernet core and saw an interesting solution
there, where a single port dist. ram (SP-RAM) was used and a state
machine was set up for up to three processes to use the single port (the
WB bus itself and two other core's processes).
As far as I can tell, the SP-RAM solution uses a simpler RAM, it's
sure there won't be any concurrent writes to the same reg, but needs a
state machine and one can not make any assumptions about a fixed time to
read its contents. On the other side the DP-RAM solution is way simpler
(doesn't need the arbiter state machine) and gives exclusive access to
the WB bus and to the core, but could run into problems with concurrent
writes to the same register.
Now I think it interesting to know and share with the community: How
do you implement this in your cores and why? Do you see any other
problems that could arise from these solutions?
Best regards!
Victor Lopez
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