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From: alessandro.poppi at tiscali.it<alessandro.poppi@t...>
Date: Wed Jul 30 09:28:34 CEST 2008
Subject: [oc] DDR IP for Spartan 3E Xilinx evakit

----- Original Message -----
From: rhoads at opencores.org<rhoads@o...>
To:
Date: Wed Jul 30 03:46:17 CEST 2008
Subject: [oc] DDR IP for Spartan 3E Xilinx evakit

> The Plasma CPU also has a simple DDR SDRAM controller for the
> Spartan
> 3E Xilinx evaluation board.

Thanks, I'm browsing the file and it looks far more "usable" than
those generated by MIG. My bus width is 8 bits instead of 32 (I see
you double-read the chip to build the needed 32 bits for your
processor) and there are a few points I need to dig to understand, but
it will certainly help. Will it work if the base frequency differs
from what you need? I have a 85MHz (dcm generated) so I may clock the
component at 42.5 and provide the x2 clock at 85.

MikeJ of fpgaarcade is also writing a ddr controller... it seems ddr
are widely used.

Ciao!
Alessandro