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Message
From: ronivon.costa at gmail.com<ronivon.costa@g...>
Date: Mon May 5 15:27:51 CEST 2008
Subject: [oc] T80 Core x
I would appreciate any help from people who used the T80 core on this.
This is more a multi-discipline problem, because it relates to Z80
assembly and VHDL:
I have this logic to read/write into memory.
DI_CPU is the Z80 input data bus.
DO_CPU is the Z80 output data bus.
A is the Z80 address bus.
The others signals are for video ram (block memory) and other devices.
This process is to store data on memory:
writevram: process(Clk_Z80)
begin
if Clk_Z80'event and Clk_Z80 = '1' then
if A >= x"2000" and A <= x"27FF" then
vram_addra_sig <= A - x"2000";
if Wr_n = '0' and MReq_n = '0' then
vram_dina_sig <= DO_CPU;
vram_wea_sig <= '0';
else
vram_wea_sig <= '1';
end if;
else
vram_wea_sig <= '1';
end if;
end if;
end process;
And this continuous assignment is to read memory and input from other
devices and send to the Z80:
DI_CPU <= D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
("0000" & SW) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) =
x"20") else
("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0)
= x"30") else
ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) =
x"80");
Now the program in Z80 assembly.
This next small program will run without problems, and the byte will
be stored in memory. I can have a buch of such commands,in sequence,
and they will run and the data will be stored in memory.
ld a,41h ; define data to store
ld (8250),a ; store the data in memory position 8250 decimal
ld a,42h
ld (8251),a
However, if I try to write a block of data, it will fail, and the data
will not be written into memory:
ld de,texto ; data to store in memory
ld bc,2000h ; address of memory to store the data
loop1:
ld a,(de) ; read 1 character
or a ; compares with zero
jr z,next1 ; if zero, then end of text
ld (bc),a ; store character in ram
inc bc ; point to next ram position
inc de ; point to next character
jr loop1 ; go to store next character
texto:
db "Testing T80 Core "
db 0
--
So, what do you think it is happening?
I have considered a T80 bug, but have not come to a definitive test to
prove that.
In the other hand, I really think there is a problem with my logic. I
am a beginner with VHDL and FPGAs.
The memory model were generated using coregenerator (xilinx) and
implemented in a Spartan 3E.
The problem does not occur when I use quartus and implement the design
on a DE1 board.
Any thoughts? Ideia? I really appreciate.
Thanks.
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