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Message
From: won.derick at yahoo.com<won.derick@y...>
Date: Wed Apr 23 04:03:54 CEST 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on TCP/IP
----- Original Message -----
From: H. Peter Anvin<hpa@z...>
To:
Date: Sat Apr 5 03:44:28 CEST 2008
Subject: [oc] FPGA based Co-processor for reducing CPU burden on
TCP/IP
processing
> Ricky James Allam wrote:
> > Hi All:
> >
> > I am new in FPGA design and am currently doing a personal
> research project on how to implement a co-processor using
> HyperTransport technology. The co-processor is to be used to reduce
> the burden of the host CPU (AMD Opteron) in processing TCP/IP
> protocols.
> >
> > Can you provide me some ideas on this to come up with a rough
> prototype of the project?
> >
> > Your help is highly appreciated.
> >
> I hate to say it, but it probably makes more sense to integrate the
> network interface -- both to reduce memory bandwidth and give you
> more
> direct control over it. At that point, you're a TOE Ethernet card.
> -hpa
>
>
The author might be thinking to include other functionality not just
simply an "offloader", like the Tarari's accelerators:
http://en.wikipedia.org/wiki/Tarari
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