OPENCORES.ORG

Q1: Are you looking for an I2C master or slave? Who drives the SCL

Based on a previous post, I'm trying to replace the Phillips I2C: PCA9564 
chip with your VHDL code.

Currently, the I2C phillips processor is the master.  

If I can ever integrate the I2C function into the FPGA, the FPGA will be 
the master.  I don't know if this will help, but if you want to contact me 
via email, maybe this process can run a little faster?  I'm sure the forum 
exists to help other people out with the same problems, but I'm thinking 
email might work faster.  I found out yesterday that I only have about 2 
weeks to get this thing done, I couldn't even go to sleep last night I 
was so stressed out.  If everybody interested in helping out is ok with 
that: jimbobsmit@g...

That's a pseudo email I created to post on the internet so my real email 
doesn't get flooded with spam or what not.  I really don't want to step 
on anybodies toes though, so if this isn't cool, that's fine, we can do 
this through the forum.

thanks, dan

----- Original Message ----- 
From: Richard Herveille<richard@h...> 
To: 
Date: Wed Mar 26 23:10:13 CET 2008 
Subject: [oc] Integrate I2C core into FPGA 

> Q1: Are you looking for an I2C master or slave? Who drives the SCL 
> signal? 
> 
> Richard 
> 
> -----Original Message----- 
> From: cores-bounces at opencores.org [mailto:cores-bounces at 
> opencores.org] On 
> Behalf Of dslaman0877 at yahoo.com 
> Sent: 26 March 2008 19:12 
> To: cores at opencores.org 
> Subject: [oc] Integrate I2C core into FPGA 
> I'm currently working on a senior project (EE undergrad) where one 
> of 
> the requirements is to replace an existing I2C chip with a coded 
> version 
> of the I2C loaded directly onto the FPGA. I really want to use the 
> I2C 
> core from this site written by Richard Herveille, but I'm really 
> confused 
> about how the whole wishbone thing works. 
> The system the I2C is interfaced with is very simple. Overall, the 
> device is a camera. I have a KODAK board (imaging sensor) connected 
> to a board that contains all the electrical components (RAM, FPGA: 
> XCV300-4PQ240C in PQFP 240 pin package, USB DLP chip, I2C chip) 
> which connects to a computer via the USB port. Matlab owns the 
> whole process, there are 2 files written that write the KODAK 
> registers 
> and the reads them (for verification) over the I2C chip. 
> I've had to reverse engineer the project, I was given a prototype, 
> told 
> to figure it out by building the whole thing from the ground up, 
> and then 
> make the changes per requirements. 
> Currently, there is a statemachine in the VHDL code that evenutally 
> outputs received signals from the FPGA to the I2C chip. The only 
> pins 
> hooked up as outputs of the FPGA to inputs of the I2C chip are: A0, 
> A1, 
> WT', RD' CE', and RST'. D0-D7 (8-bit data line) is hooked up to the 
> I2C 
> as bi-directional data. Finally, I have the SCL and SDA lines 
> hooked up 
> to the Kodak board. 
> My idea was to redefine the outputs of the FPGA as internal signals 
> that 
> would map to the I2C core signals. I think that the clock 
> everything is 
> running off of needs to be mapped to the clock signal in the I2C 
> core as 
> well. I know I'm asking for a whole lot of help here, but I'm 
> really 
> running out of places to turn to. thanks 
> _______________________________________________ 
> http://www.opencores.org/mailman/listinfo/cores 
> 
> 