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Message
From: Attila Kinali<attila@k...>
Date: Sat Feb 23 09:51:32 CET 2008
Subject: [oc] PCI core question
On Sat, 16 Feb 2008 17:00:22 -0800
Howard Harte <opencores@d...> wrote:
> One issue I'd like some advice on is improving read latency. For
> single 32-bit writes, they complete in about 300ns, which is fine.
> For 32-bit reads, they complete in 2.5uS, which is a really long
> time. I'm reading and writing to a FIFO, which occupies a single
> address on the wishbone backplane.
You might want to give the PCI core from OGP a look.
It was written from scratch because the OC PCI core
was not fast enough. But there are two catches:
1) Although it has been tested, there has AFAIK no
trough out test in different setups and PCs, so
there migh be some compatibility issues lingering.
2) Because wishbone was deemed too slow for OGP,
they use their own internal bus. So you would
have to write some glue logic there.
Attila Kinali
--
The true CS students do not need to know how to program.
They learn how to abstract the process of programming to
the point of making programmers obsolete.
-- Jabber in #holo
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