LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Thomas Winkler<tc@t...>
    Date: Fri Feb 8 11:30:09 CET 2008
    Subject: [oc] I2C core questions (Avalon, SOPC)
    Top
    Hello,

    > It's generally good practice to _NOT_ have any bidir ports in your design
    > except for the topmost level. Technically, internal bidir ports can't be
    > synthesized anyway, and synthesis tools just make it look like you can.
    > The way this is done has changed in Quartus, for example, in the last few
    > versions and has caused problems with some older designs that I have
    > re-built recently.

    Ok - that means that I should not have scl and sda as inout ports in my
    i2c_master_top_avalon.vhd file? My idea was to add the tri-state logic to
    this file and define the ports as "inout" since i do not intend to use SCL
    and SDA internally anyway but bring them out to the board pins.

    > [...] I wanted to use it to (also)
    > interface to on-chip peripherals, and so had to change the interface.

    Ok - that absolutely makes sense to me. But since I (for now) only intend to
    interface off-chips peripherals my code should be ok, right?

    > Maybe this is related to my comment above??? I'm assuming you have a
    > top-level wrapper around the SOPC-generated VHD - yes? What type of port
    > do you have specified for SCL/SDA there? If not, it's generally a good
    > idea to do so...

    Yes - but my toplevel wrapper is a schematic but not a VHDL file. But the
    principle should be the same. In my previous version I hat a mistake
    regarding the SCL and SDA ports in the schematic. Now the are bidi ports as
    they should be. See: http://www.wnk.at/tmp/i2c/toplevel.png

    > The cyclone parts have a weak internal pullup option which you need to
    > specify in the assignments editor - IIRC around 22K? Depending on your
    > external bus/peripheral that may or may not be sufficient.

    Ok - I now found out how to set the pull-up in the pin assignment editor:
    http://www.wnk.at/tmp/i2c/pin_assignment_2.png
    I now measure ~3.1V on the idle SDA pin but get 0V on the SCL pin which
    confuses me. I'm not sure whats wrong with this one.
    Do you have any idea?

    Thank you,
    --
    Thomas Winkler
    tc@t...

    ReferenceAuthor
    [oc] I2C core questions (Avalon, SOPC)Mark McDougall

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.