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Message
From: cgj at rediffmail.com<cgj@r...>
Date: Mon Nov 19 16:50:41 CET 2007
Subject: [oc] free DES core in Verilog
Hello Friend,
I'm also in need of free DES core in Verilog. If u had got, can u pls
send it to me.
Regards, Govind.
----- Original Message -----
From: "Rudolf Usselmann" <russelmann@h...>
To: cores@o...
Date: Tue, 18 Jul 2000 23:56:50 PDT
Subject: [oc] DES Core
>
>
>
> I just checked in a DES core I wrote.
>
> Here is the biref readme file, sorry the documentation
> is very short. See the test bench (des_test.v) files,
> they should help understand how to use the block ...
>
> Everything is in Verilog ...
>
> rudi
>
>
> DES Core
> ========
>
> Attached is a DES core implementation in verilog. It takes a
> standard
> 56 bit key and 64 bits of data as input and generates a 64 bit
> encrypted/decrypted result. Two implementations are provided:
>
> 1) Area Optimized (CBC Mode)
> This is a sequential implementation and needs 16 cycles to
> complete
> a full encryption/decryption cycle.
> It is about 5.5K gates large and runs at about 66Mhz in a Xilinx
> Vertex -4 FPGA
>
>
> 2) Performance Optimized (EBC Mode)
> This is a pipelined implementation that has a 16 cycle pipeline
> (plus 1 input and 1 output register). It can perform a complete
> encryption/decryption every cycle.
> It is about 40K gates large. In an Xilinx Vertex -4 it runs at
> about 75Mhz in an VirtexE -8 about 100Mhz. All synthesis was
> done
> with Synopsys FPGA Compiler II.
>
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