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Message
From: Miha Dolenc<mihad@o...>
Date: Wed Nov 14 16:19:41 CET 2007
Subject: [oc] A Virtex-5 slice utilization problems
Try removing "default:" line from case statement.
I know it's a long shot, but ISE 9 tools are very bugy
and maybe xst doesn't determine correctly that you have all
input combinations covered.
Regards,
Miha Dolenc
----- Original Message -----
From: "Umair Siddiqui" <umairsiddiqui84@g...>
To: "Discussion list about free open source IP cores" <cores@o...>
Sent: Wednesday, November 14, 2007 1:00 PM
Subject: [oc] A Virtex-5 slice utilization problems
> According Virtex 5 User Guide (ug190.pdf):
> -----------------------------------------------------
> Each slice has an F8MUX. F8MUX combines the outputs of F7AMUX and
> F7BMUX to form a combinatorial function up to 27 inputs (or a 16:1
> MUX). Only one 16:1 MUX can be implemented in a slice, as shown in
> Figure 5-23.
> ===========================================
> Now I code
>
> module mux16
> (
> input clk,
> input [3:0] sel,
> input [15:0] in,
> output reg q
> );
>
> always @(posedge clk) begin
> case (sel)
> 4'd0 : q <= in[0 ];
> 4'd1 : q <= in[1 ];
> 4'd2 : q <= in[2 ];
> 4'd3 : q <= in[3 ];
> 4'd4 : q <= in[4 ];
> 4'd5 : q <= in[5 ];
> 4'd6 : q <= in[6 ];
> 4'd7 : q <= in[7 ];
> 4'd8 : q <= in[8 ];
> 4'd9 : q <= in[9 ];
> 4'd10 : q <= in[10];
> 4'd11 : q <= in[11];
> 4'd12 : q <= in[12];
> 4'd13 : q <= in[13];
> 4'd14 : q <= in[14];
> 4'd15 : q <= in[15];
> default: q <= 1'b0;
> endcase
> end
>
> endmodule
> ===========================================
> I'm getting following result using Xilinx ISE 9.2.02i (IO buffers are
> not required) => 6 slices
>
> and also notice there is no F8MUX!
>
> ================================
> * Final Report *
> ================================
> Final Results
> RTL Top Level Output File Name : mux16.ngr
> Top Level Output File Name : mux16
> Output Format : NGC
> Optimization Goal : Area
> Keep Hierarchy : NO
>
> Design Statistics
> # IOs : 22
>
> Cell Usage :
> # BELS : 7
> # LUT3 : 1
> # LUT6 : 4
> # MUXF7 : 2
> # FlipFlops/Latches : 1
> # FD : 1
> =================================
>
>
> Device utilization summary:
> ---------------------------
>
> Selected Device : 5vlx220tff1738-2
>
>
> Slice Logic Utilization:
> Number of Slice Registers: 1 out of 138240 0%
> Number of Slice LUTs: 5 out of 138240 0%
> Number used as Logic: 5 out of 138240 0%
>
> Slice Logic Distribution:
> Number of Bit Slices used: 6
> Number with an unused Flip Flop 5 out of 6 83%
> Number with an unused LUT: 1 out of 6 16%
> Number of fully used Bit Slices: 0 out of 6 0%
> Number of unique control sets: 1
>
> IO Utilization:
> Number of IOs: 22
> Number of bonded IOBs: 0 out of 680 0%
>
> ===========================================
> Problem is that I need to make a arbiter handling 64 requesters @ 250
> Mhz. I was estimating that 64 bit 64:1 (with registered intermediate
> stages) should take 64*5=320 slices. I've not yet started coding...but
> it seems useless :-(
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
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