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Message
From: g-sus at gmx.li<g-sus@g...>
Date: Thu Jun 28 17:56:54 CEST 2007
Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL
> Make sure you keep the control signals asserted until you get a
> cmd_ack from ...
so we can't use a code like this to check for the next state ?
( similar to the DS1621 Sample Code)
[code]
when i2 => -- send "access config"
command
if (cmd_ack = '1') then
nxt_state := i3;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no
acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := x"AC";
end if;
[/code]
We noticed that the cmd_ack bit ( mapped to the cmd_ack bit of the
byte controller) never gets 1 (but it schould get set through the bit
controller). Is this a timingproblem, or is this approach completly
wrong ?
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