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Message
From: g-sus at gmx.li<g-sus@g...>
Date: Tue Jun 26 19:17:16 CEST 2007
Subject: [oc] I2C clock timing / Masterbyte Controller / VHDL
Hello, We are trying to use the i2c_master_byte_ctrl.vhd (and the bit
controller of course) without the wishbone Interface and trying to
develop a test state machine like in the "State machine for reading
data from Dallas 1621" sample.
We are using the following ports of the MAsterbyte Controller
[code]
clk => clk, -- Byte => bit
ena => ena,
rst => rst,
scl_i => scl_i,
sda_i => sda_i,
clk_cnt => clk_cnt,
nReset => nReset,
read => read,
write => write,
start => start,
stop => stop,
ack_in => ack,
cmd_ack => cmd_ack,
din => D,
dout => Dout,
ack_out => lack,
scl_oen => SCL,
sda_oen => SDA
[/code]
But when starting the whole process, the SDA line signales a start ,
then the address + r/w is correctly added together by the
byte_controller, but the transmission is stopped through a stop
signal. This procedure repeats infinite times ..
Does someone have an idea why this occures ?
thanks
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