LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cores > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: Guy Hutchison<ghutchis@g...>
    Date: Mon Jun 25 20:35:29 CEST 2007
    Subject: [oc] Problem with T51 core & Xilinx ISE
    Top
    Hi Andreas,

    Doesn't sound normal. I used to run synthesis of the TV80 core (similar
    size) + DUT into a Virtex-4 device, and synthesis was on the order of 5
    minutes. Going from a new netlist to a BIT file took less than an hour.

    It will probably use distributed RAM because register files and various
    other parts are async read. The TV80 uses relatively small amounts of it,
    but the T51 may have significantly more.

    The only non-standard thing I did was to run the whole process from the
    command line.

    - Guy

    On 6/25/07, attachment.htm

    ReferenceAuthor
    [oc] Problem with T51 core & Xilinx ISEX-opencores org

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.