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Message
From: Guy Hutchison<ghutchis@g...>
Date: Wed May 16 19:42:36 CEST 2007
Subject: [oc] Veilog 2001 cores
I haven't seen much relunctance to learn Verilog-2001. Most of it is pretty
straightforwards, and makes writing your code easier.
What I have seen is that tool vendors were very slow to add support for 2001
features, and did so piecemeal, with the result that designers are unwilling
to use the new features because the benefit is slight (if you've been using
Verilog a while, you figured out other ways to do the same thing), and it's
unclear what tools later in the pipeline will break.
I started using some of the basic 2001 statements 3-4 years ago, and
although I used only the simplest statements (@* and inline port lists), I
still ran into problems with tools in the flow that couldn't parse the
netlist or gave incomplete support.
Generate? Bah. That's what Perl/Python is for.
- Guy
On 5/16/07, Nikolaos Kavvadias <attachment.htm
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