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Message
From: des00 at opencores.org<des00@o...>
Date: Fri May 11 14:07:08 CEST 2007
Subject: [oc] Question on Ethernet MAC 10/100 Mbps
Hi all! There is more simple variant, the truth it demands more time and require
reverse engeneering experience.
It is possible to cut out from IP all units concerning to a host interface
and will leave only
the transmitter and the receiver management signals . In total such
signals is 12:
TxClk, TxUsedData : in std_ulogic;
TxData : out std_logic_vector (7 downto 0);
TxStartFrm, TxEndFrm : out std_ulogic ;
TxUnderRun : out std_ulogic ;
-- eth_top Rx interface
RxClk : in std_ulogic ;
RxData : in std_logic_vector ( 7 downto 0);
RxValid : in std_ulogic ;
RxStartFrm, RxEndFrm : in std_ulogic ;
TxPauseReq : out std_ulogic
After that it is possible to connect to these signals anything you like.
For example 2 FIFO and FSM which will operate transfer and reception.
Thanks Igor Mohor, his verilog code is reading clearly enough and
simply.
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