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Message
From: juergen.sauermann at t-online.de<juergen.sauermann@t...>
Date: Thu May 10 19:33:50 CEST 2007
Subject: [oc] White Noise generator
Hi,the following solution claims to be quite efficient in terms of slices: http://www.eecs.berkeley.edu/Programs/ugrad/superb/papers2003/Mustapha%20Abdulai.pdf
----- Original Message -----
From: jeanpaul.milani at amicweb.com<jeanpaul.milani@a...>
To:
Date: Fri Apr 20 21:53:17 CEST 2007
Subject: [oc] White Noise generator
> Hi
> I'm approcing to realize a white noise generator
> using a Lattice fpga and a pcm1793 dac @ 192KHz
> I've found many solutions on the web but many of them
> are too slice's expencive for me.
> I've try with a lfsr using this code:
> entity wgn is
> port(
> clk_24 : in std_logic;
> rst : in std_logic;
> en_192 : in std_logic;
> wgn_out : out std_logic_vector (23 downto 0);
> data_valid : out std_logic
> );
> end;
> architecture rtl of wgn is
> signal sh_reg : std_logic_vector(23 downto 0);
> signal data_valid_int : std_logic;
> begin
> process(clk_24,rst)
> begin
> if rst = '1' then
> wgn_out <= (others => '0');
> sh_reg <= (others => '1');
> data_valid_int <= '0';
> data_valid <= '0';
> elsif (clk_24'event and clk_24 = '1') then -- Rising edge for clk24
> if en_192 = '1' then
> sh_reg(sh_reg'high downto 1) <= sh_reg((sh_reg'high-1) downto
> 0);
> sh_reg(0)<= sh_reg(23) xor sh_reg(7) xor sh_reg(2) xor
> sh_reg(1);
> data_valid_int <= '1';
> else
> data_valid <= data_valid_int;
> data_valid_int <= '0';
> wgn_out <= sh_reg;
> end if;
> end if;
> end process;
> end rtl;
> when i've try the machine i've notice that the power spectrum isn't
> flat
> but it's quite gaussian with a peak @ 20KHz.
> I hope someone can help me
> thanks
>
>
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