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From: heedaf at excite.com<heedaf@e...>
Date: Mon May 7 05:20:39 CEST 2007
Subject: [oc] Xilinx ISE
With ISE are we required to input delays for for components for the
behavioral analysis or is it built into the software? If so, how do I
simulate delay for the pre-built memory?
Thanks,
Dewayne