|
Message
From: digitalhomesolutions at cox.net<digitalhomesolutions@c...>
Date: Tue May 1 01:19:06 CEST 2007
Subject: [oc] I2C SR Question
Richard,
My mistake! I meant to ask when does the SR[7] (slave ack) get set
high.
Thanks,
Steve
----- Original Message -----
From: Richard Herveille<richard@h...>
To:
Date: Mon Apr 30 20:43:15 CEST 2007
Subject: [oc] I2C SR Question
> The 'ack' in the example below is the wishbone acknowledge.
> It is not the i2c acknowledge.
> Richard
> -----Original Message-----
> From: cores-bounces at opencores.org [mailto:cores-bounces at
> opencores.org] On
> Behalf Of digitalhomesolutions at cox.net
> Sent: Monday, April 30, 2007 11:19 PM
> To: cores at opencores.org
> Subject: [oc] I2C SR Question
> Since the following code from the test bench looks for the ack to
> go low
> when does bit 7 of of the status register get set to high?
> Thanks,
> Steve
> // wait for acknowledge from slave
> while(~ack) @(posedge clk);
> // negate wishbone signals
> #1;
> cyc = 1'b0;
> stb = 1'bx;
> adr = {awidth{1'bx}};
> dout = {dwidth{1'bx}};
> we = 1'hx;
> sel = {dwidth/8{1'bx}};
> d = din;
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores
>
>
|
 |
Browse
