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Message
From: Richard Herveille<richard@h...>
Date: Mon Apr 30 20:43:15 CEST 2007
Subject: [oc] I2C SR Question
The 'ack' in the example below is the wishbone acknowledge.
It is not the i2c acknowledge.
Richard
-----Original Message-----
From: cores-bounces@o... [mailto:cores-bounces@o...] On
Behalf Of digitalhomesolutions@c...
Sent: Monday, April 30, 2007 11:19 PM
To: cores@o...
Subject: [oc] I2C SR Question
Since the following code from the test bench looks for the ack to go low
when does bit 7 of of the status register get set to high?
Thanks,
Steve
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
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