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Message
From: digitalhomesolutions at cox.net<digitalhomesolutions@c...>
Date: Mon Apr 30 23:18:42 CEST 2007
Subject: [oc] I2C SR Question
Since the following code from the test bench looks for the ack to go low
when does bit 7 of of the status register get set to high?
Thanks,
Steve
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
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